IBM is building the world’s first fault-tolerant quantum computer, IBM Quantum Starling. Slated to launch in 2029, Starling will be capable of running quantum circuits comprising 100 million quantum operations on 200 qubits.
The framework for Starling was described in a 2025 paper, which presented a path to achieve fault tolerance by creating hardware to implement the bivariate bicycle quantum low-density parity check (qLDPC) error correction codes introduced by IBM in a 2024 Nature publication. Critically, the code is implemented in a modular fashion to enable scalability beyond what could be achieved with a monolithic architecture.
The modular architecture detailed in the paper offers an order of magnitude reduction in resource requirements compared to prior approaches. For the same logical error rate, Starling’s qLDPC architecture requires about 10x fewer physical qubits. It is constructed by assembling modules that each contain a quantum memory and logical processing unit (LPU), which allows logic operations on the memory. The modules have universal adapters that allow them to be connected using l-couplers. Additionally, sophisticated modular cryogenic and control systems house and run the modules at ultra-cold operating temperatures.
Below, we provide an update on significant technical advances toward Starling, broken down into six categories. These steps forward are being delivered in parallel, though not in isolation — lessons from one component influence the progress being made on the others. Taken together, the work outlined below represents major progress toward building Starling and delivering on the promise of fault-tolerant quantum computing.
Device physics
IBM Quantum Loon was announced a year ago to demonstrate many of the key components needed to implement IBM’s qLDPC codes, including qubit reset circuits and “c-couplers” to link qubits across the chip, a prerequisite for establishing the six-way qubit connectivity needed to implement the qLDPC code.
Since then, Loon was measured to have qubit relaxation times (T1) of about 200us with reset time constants of 20ns–40ns. Its gates had median error rates near 0.3%. The ultimate aim for Starling is to have T1 in the millisecond range and gate errors in the low 0.01% range. The physics of the device are designed to enable this low error rate. In fact, we routinely measure gate errors in the high 0.01% range on Heron and Nighthawk — going as low as 0.04%. Transferring coherence times from our test devices, which are currently in the single digit millisecond range, will also help facilitate lower error rates.
It is also important to understand how much loss the c-coupler layers introduce so we can estimate gate error limits. The results here are also very promising. The resonators had quality factors above 10 million, which is beyond the goal needed for Starling. Adding to this, it was found that traversing c-coupler layers only resulted in a minimal reduction in quality factor, meaning it was possible to increase the number of c-coupler layers being used in the chip. Originally two were being used, but that has now increased to three with plans to reach four or more. Adding additional layers will enable more complex routing and can effectively shorten some of the longest connections c-couplers need to make.
The results above verify that c-couplers are a viable approach to enabling non-local, dense connections for quantum processors.
QPUs
Advances have also been made in how quantum processing units (QPUs) can be put together.
In particular, there have been two exciting developments related to overall device yield and complexity. First, improvements to the qLDPC code made it possible to have only five connections between qubits instead of six — while also delivering 20x-100x lower logical errors. Second, with further coupler innovations, we discovered ways to reduce the number of Josephson junctions. Bringing these advances together, the number of Josephson junctions needed has been more than cut in half, dropping from around 5,000 to 2,000.
This junction reduction means that our device yield will increase. With a junction yield target of 99.95%, we find that about 1 out of 12 processors will be fully functional with 5,000 junctions, but 1 out of 3 processors will be fully functional with 2,000 junctions — a factor of 4x increase. Having fewer junctions will also help lower the spread of required critical junctions across the device.
Lastly, the length of the c-coupler has been increased to 20mm, which helps loosen some of the strict density requirements of qubits and couplers on a quantum processor.
This combination of exciting results demonstrating high quality factors within and across c-couplers, the improved code, and device yield improvements led us to redesign the modular processors. The new designs lower the risk and increase yield for the modular qLDPC code processors and hence will benefit Starling. A year ago, it would not have been possible to envision this, showcasing how ongoing innovation pushes us toward ever better designs.
Modular decoders
Decoders, classical algorithms used to identify errors in quantum circuits, are needed to achieve fault-tolerant quantum computing. IBM introduced the decoder Relay-BP in 2025 and showed that it could deliver a better logical error rate than leading alternatives while simultaneously lowering compute requirements for decoding. Now, IBM researchers have extended Relay-BP to demonstrate that errors for memory-only operations and measurement operations are nearly consistent. In fact, the performance we observe already meets the requirements for Starling.
To run Relay-BP on Starling, IBM is creating a real-time decoder ASIC leveraging 2nm nanosheet technologies. This custom chip will deliver improved logical error rates to increase Starling’s performance.
Inter-module connectivity
To scale to a large number of error-corrected qubits, the processing modules for Starling need to be linked with long-range connections called l-couplers.
IBM recently connected two Nighthawk processors using four l-couplers, as described in this paper, achieving an average 1% error rate with the best result being 0.7%. Linking multiple Nighthawk processors together is a crucial step toward scaling to larger systems that can do useful work. These results were enabled with high quality factor coaxial cables with magnetic shielding and a Q exceeding 1 million. Relative to prior demonstrations, the raw error rates have improved by about a factor of 2x, but the key outcome is the repeatability of attaching l-couplers to processors. We learned that magnetic shielding is important but also that the usual concerns related to thermalization and vibrations matter. Everything must be assembled in a way that does not undo careful microwave engineering so that coupling strengths and dephasing rates are consistent.
Starling will ultimately need over 100 l-couplers per module with 0.1% error rates. This is why progress on improving reliability and repeatability is an important step.
Modular cryogenics and wiring
To reach the scale needed for Starling, the cryogenic environments used to house the quantum processors have to be able to seamlessly link processing modules together. This year, IBM addressed this challenge by introducing a modular cryogenics design that will form the backbone of its future quantum systems.
These modular cryostats are rectangular in design — as opposed to the previously used cylindrical cryostats — to make it easier to connect to neighboring units. We paid careful attention to making sure the cooling engine (the cryostat insert) is separate from the vacuum shell, which is also separate from the shielding and wiring. This makes it possible to more reliably assemble many units together. Additionally, the design includes dedicated pathways for l-couplers to traverse the cryogenic space to connect processors across different cryostats.
The processors in these systems will require many control lines to control each qubit and coupler. Each cryostat bay is designed to carry as much as 0.96 miles of trace length. Only 0.86 miles will be necessary for Nighthawk r2, but Nighthawk r3 will use about 3.84 miles of trace length. This massive amount of trace wiring could not have been achieved without multiple iterations to go from coaxial lines to flex, and then finding improvements across several flex designs.
As of November 2026, two Nighthawk r2 devices attached with l-couplers are cooling in these cryostats. The very latest data shows l-coupler quality factors in the usual range of 1-2 million. This represents good progress toward Starling, which will need up to twelve cryogenic modules connected together.
Modular control electronics
Control electronics are a key part of running a quantum system. Typically, these are handled by room-temperature computers, but getting signals into and out of the ultra-cold cryogenic environments adds a lot of bulky wiring to systems and introduces noise that can disrupt the state of qubits. To support Starling’s level of performance, new control systems will be needed that act in real-time and exhibit better noise performance.
One approach to achieving this is finding a way to run control electronics using chips inside the cryostat itself, removing the additional wires, sources of heat, and signal bottlenecks.
IBM recently created new application-specific integrated circuits (ASICs) for cryogenic control that match the performance of room-temperature control electronics. We previously showed the ability to control around half of the two-qubit gates on a Heron processor with ASIC control — single-qubit gates were still generated by room-temperature control electronics. With the latest version of the ASIC, we continued to refine noise characteristics and now match and even exceed the gate performance compared to room-temperature control only. This is a major step forward.
Ultimately, Starling will require a modular real-time control system built on diverse classical information flows, as outlined in the diagram below. This logical control architecture extends Starling’s modular design into the control layer, combining CPUs, field-programmable gate arrays (FPGAs), and ASICs. A critical enabler of this will be interconnect technologies that are scaled to large systems without undermining key considerations like latency. This year, we have validated through small-scale prototypes that several standards-based interconnect technologies satisfy the requirements for Starling’s control system.
The outlook on the path to IBM Quantum Starling
The advances discussed above represent major progress toward Starling:
- The c-coupler approach has been validated.
- The number of qubit connections and Josephson junctions required has been greatly reduced.
- IBM’s decoder algorithm has reached the performance needed for Starling.
- Quantum processors have been linked using l-couplers with improved repeatability.
- A new modular cryogenic system has been launched and tested.
- IBM’s ASICs for cryogenic control were found to match the gate performance of room-temperature electronics.
While the updates described above are important, they reflect only some of the key achievements on the path to Starling. For example, progress continues to be made around refining our LPUs and reducing the overhead associated with magic state injection. The main architecture for Starling has not changed.
Starling is still a few years away, but the pathway IBM has chosen has been validated and points to clear next steps for further progress.
