Key Takeaways:
- The U.S. Department of Energy’s Quantum Science Center (QSC) at Oak Ridge National Laboratory (ORNL), IBM, and AMD deployed a co-design platform for quantum error correction (QEC) at IBM's site in Poughkeepsie, New York.
- The QEC co-design platform pairs IBM Quantum Nighthawk r2 processors with ORNL’s Umbra High-Performance Computing (HPC) system, comprising AMD Instinct MI355X GPUs and 5th Gen AMD EPYC™ CPUs.
- Researchers can use the platform to develop and validate quantum algorithms, workflows, and applications for hybrid HPC-quantum computing environments without building the infrastructure themselves.
- Quantum error correction depends on decoders, the classical software that identifies qubit errors and must keep pace with the quantum processor.
- Placing ORNL’s hardware next to the IBM quantum processors gives the system low-latency quantum-classical execution.
Oak Ridge National Laboratory (ORNL), IBM, and AMD have launched a co-design platform for quantum error correction to help researchers define and accelerate the classical and quantum workflows for scientifically relevant quantum computing.
The quantum error correction (QEC) co-design platform sits at IBM's site in Poughkeepsie, New York and launched with the U.S. Department of Energy’s Quantum Science Center (QSC) at ORNL and AMD as its inaugural partners. It pairs IBM Quantum Nighthawk processors with Umbra, QSC’s high-performance computing system comprising AMD Instinct MI355X GPUs and 5th Gen AMD EPYC™ CPUs, in one co-located environment linked to ORNL's broader supercomputing ecosystem.
This initiative brings together the computing infrastructure needed for quantum error correction in a single environment and opens it up to more researchers than ever before. They will use it to develop and validate quantum algorithms, workflows, and applications in an environment designed for quantum-centric supercomputing, an emerging paradigm where quantum processors, CPUs, and GPUs work together as one system. The platform handles the infrastructure, so researchers can concentrate on algorithm discovery.
A co-design platform for quantum error correction
This platform builds on IBM and AMD's existing collaboration, including using AMD GPUs to accelerate sample-based quantum diagonalization and demonstrating efficient quantum error decoding on AMD hardware. The collaboration will also explore how future generations of AMD compute, networking and open software can be co-designed with quantum computers.
How the co-design platform will advance quantum computing research
Qubits, the fundamental units of quantum computation, make errors. Quantum error correction protects against them. Error correcting codes spread information across many qubits and run repeated checks for signs of trouble. A classical computer reads the data from each round of checks and works out which errors occurred. Researchers call the software that does this job a decoder, and it has to keep up with the quantum processor. That’s a fast-paced, demanding, computationally-intensive task.
The algorithms that will make quantum computing scientifically useful need substantial classical computing resources working in step with quantum processors. Today, quantum computers and high performance computing (HPC) infrastructure rarely sit in the same location or get directly integrated. That means that researchers working on hybrid workflows often stitch those pieces together themselves. They reach a quantum computer through the cloud, run classical work on separate systems, and connect the two through separate application programming interfaces (APIs), the software links that let one system talk to another. Every handoff adds complexity and delay, and limits the experiments researchers can run.
Error correction lays the foundation for practically relevant quantum computing. Its value comes from what it unlocks: larger, deeper, more capable quantum computations. The QEC co-design platform lets researchers test error correction on real quantum systems, inside the workflows it will serve. It also enables researchers to explore the use of GPUs for low-latency decoding more broadly.
One promising approach is hierarchical error correction, and the platform could support research in that direction. The hierarchical approach layers two codes. An inner code protects qubits within a module. An outer code wraps around the inner code’s logical qubits and adds a second layer of protection. The inner code’s own logical operations supply the long-range connections the outer code needs, so the code itself provides the added protection and the chip stays simpler.
Recent IBM research found that this approach could reach a trillion logical operations at a physical error rate of one in a thousand. These hierarchical codes rely on powerful classical computing. Decoding happens at each layer, and results from one layer feed into the next. The co-design platform gives researchers a place to test and develop those ideas with GPUs in a low-latency environment.
With quantum and classical components in a shared environment, the codesign platform will enable researchers to explore quantum-classical workflows with the classical compute those workflows depend on, without building that infrastructure themselves. They can develop, test, and refine quantum algorithms, investigate error correction approaches, and gain early insight into what future error-corrected machines will require. Those insights can help inform the architectures, software, and workflows that will advance future systems.
The platform aligns with the U.S. Department of Energy’s Genesis Mission, which aims to deploy a scientifically-relevant quantum computer by 2028. Experiments have now run up to 70 logical qubits—qubits protected by error correction—through 438 difficult operations. The Genesis Mission’s Q Competition targets 100 logical qubits running 100,000 such operations by late 2028. That’s a roughly 230-fold jump.
How the platform works
The platform uses the most advanced hardware from both IBM and AMD.
On the quantum side are Nighthawk r2 processors. They can run circuits beyond the reach of brute-force classical simulation. Nighthawk gives error correction researchers square-lattice connectivity—the highest connectivity of any IBM quantum processor architecture today—high circuit throughput, and real-time pulse control. Researchers can measure qubits mid-calculation, act on the results in real time, and work directly with raw measurement signals. That lets teams compare what each error correction method demands in qubits, time, and classical computing, and find where AMD GPUs help most.
On the classical side, Umbra combines ORNL’s AMD Instinct MI355X GPU accelerators with dedicated 5th Gen AMD EPYC™ CPUs. The GPUs let researchers train and evaluate decoders at large scale and explore error correction approaches that may make future systems more efficient. All this work will inform the development of IBM Quantum Starling, the fault-tolerant quantum computer IBM plans to deliver by 2029.
Because the classical compute sits next to the quantum processors, the system is optimized for low-latency quantum-classical execution, with short delays as data moves between them. Low latency matters for decoding and for conditional execution, where a quantum program picks its next operation based on a measurement taken mid-computation. That fast feedback will support workflows like those required by hierarchical codes.
This is the infrastructure of quantum-centric supercomputing in action.
